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Honored Contributor
Honored ContributorClocked process triggered by pulse signal (VHDL question)
What I would like to do is to execute a clocked process whenever the rising edge of a pulse arrives. Here is my code:
process (pulse, clk)
variable newTrigger: std_logic:='0';
variable cnt: int...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Using a "rising_edge" function basically uses the specified signal as a clock. In an FPGA you can only use 1 clock per process. But your code is rather confusing, because according to your code, even if you could use two clocks, as soon as there was a rising edge of pulse, newTrigger is instantly set back to '0'. So how did you expect it to work? --- Quote End --- What I want to do is that the variable "cnt" can be set to 32 once after a rising edge of pulse arrives. Setting newTrigger instantly back to 0 is to ensure that "cnt" is set to 32 only once.
