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Altera_Forum's avatar
Altera_Forum
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15 years ago

Clock division and multiplexing in Cyclone-I

Hello all,

I have Cyclone-I FPGA in my lab. It is: EP1C12Q240C6.

My requirement is to be able to select between 2 different crystal clocks, and their divide-by-2, divide-by-4 and divide-by-8 versions. This means that I need to have a selection for 8 different frequencies. On my board, I have two crystals with frequencies of 100MHz and 160MHz.

From documentations, I see that Cyclone FPGA doesn't support the altclkctrl megafunction. This is unfortunate!

Then I went through the Cyclone handbook on clock management. I see that at the output of the PLL, there is a multiplexer for selecting between the pll-input clock (inclk), pll-generated clocks (c0), dual-purpose clocks (dpclk) and user generated clocks. But it is not mentioned how one goes about using this multiplexer. can someone please tell me how one can use the internal clock multiplexer?

In my device, there are two PLLs. I am planning to connect the 160MHz crystal to the first PLL for generating 80MHz and 40Mhz, and then have an internal logic for 20Mhz. In the same way, I plan to connect 100MHz to the other PLL for generating 50MHz and 25MHz, and create logic for 12.5MHz.

Now the problem is, how do I multiplex all these to get a single clock output. I am thinking of using the second PLL and its associated multiplexer for driving the 100MHz related clock out of the chip, back to a DPCLK input of the first multiplexer (160MHz related). I don't see any other way for doing this. Can someone please help me out with this.

thanking in advance,

rajesh

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Have you considered using clock enable.

    You run 100 and 160 clocks without PLL.

    You design two clock domains one at 100 and the other at 160.

    For any logic running at 1/2,1/4 or 1/8 of its clock speed you simply provide clock enable regulary pulsed every other clock(for 1/2), every 4th clock(for 1/4) and every 8th clock(for 1/8).

    If you have to select only one rate among all above then run all on 160 and produce clock enable accordingly. for 100,100/2,100/4,100/8 you can use modulo adder to generate clock enable. I suggest the modulo adder running 0~319 counts as follows:

    to get 100MHz: increment by 200

    to get 50MHz: increment by 100

    to get 25MHz:increment by 50

    to get 12.5MHz:increment by 25

    at overflow, generate one enable pulse. All you need is to get detect overflow correctly. but take care to add the increment carefully at this overflow.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Kaz,

    Thank you very much for the response. Actually, I need to drive the generated data along with the selected clock out of the chip. So I can't use clock enables, because I need an actual running clock for driving out. Can you kindly suggest some other way around.

    regards,

    rajesh
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If you want to avoid timing problems I suggest you approach with a two perspectives: Fpga Internal processing & driving clock out.

    For internal processing use clock enable as stated before. This is very simple to run on 160MHz then all you need is only change the increment value of your 320 modulo adder as illustrated below:

    incr : 320 => 160MHz rate (or '1' always) = 160 320/320

    incr : 160 => 80MHz rate = 160 x 160/320

    incr : 80 => 40MHz rate = 160 x 80/320

    incr : 40 => 20MHz rate = 160 x 40/320

    incr : 200 => 100Mhz rate = 160 x 200/320

    icrr : 100 => 50MHz rate = 160 x 100/320

    incr : 50 => 25MHz rate = 160 x 50/320

    incr : 25 => 12.5MHz rate = 160 x 25/320

    For clocking out:

    use your PLLs to generate the 8 clocks. use two PLLs, one for each clock input or use one pll if it can generate all 8 clocks. Then you can select out any clock you want. clock mux is not necessary for driving clock out. It is meant for internal use.

    If you get io timing problems then consider using dc fifo to bridge data over, the safest way is to have 8 fifos each just few words deep.

    each fifo is connected to its write clk and clk enable and its separate read clock from PLL then you only switch data out
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    From documentations, I see that Cyclone FPGA doesn't support the altclkctrl megafunction. This is unfortunate!

    Then I went through the Cyclone handbook on clock management. I see that at the output of the PLL, there is a multiplexer for selecting between the pll-input clock (inclk), pll-generated clocks (c0), dual-purpose clocks (dpclk) and user generated clocks. But it is not mentioned how one goes about using this multiplexer. can someone please tell me how one can use the internal clock multiplexer?

    --- Quote End ---

    You can't configure this mux at runtime. This mux is part of the current FPGA configuration. You can't change the mux setting without reconfiguring the whole FPGA.

    --- Quote Start ---

    Now the problem is, how do I multiplex all these to get a single clock output.

    --- Quote End ---

    It depends on your mux and clock requirements. Can you afford glitches when switching between different clocks? If you can, then a simple combinatorial logic selection can be used.

    If you can't, then you would need to register the clock selection. This might get complicated unless you can use a single master clock.