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From documentations, I see that Cyclone FPGA doesn't support the
altclkctrl megafunction. This is unfortunate!
Then I went through the Cyclone handbook on clock management. I see that at the output of the PLL, there is a multiplexer for selecting between the pll-input clock (inclk), pll-generated clocks (c0), dual-purpose clocks (dpclk) and user generated clocks. But it is not mentioned how one goes about using this multiplexer.
can someone please tell me how one can use the internal clock multiplexer? --- Quote End ---
You can't configure this mux at runtime. This mux is part of the current FPGA configuration. You can't change the mux setting without reconfiguring the whole FPGA.
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Now the problem is, how do I multiplex all these to get a single clock output.
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It depends on your mux and clock requirements. Can you afford glitches when switching between different clocks? If you can, then a simple combinatorial logic selection can be used.
If you can't, then you would need to register the clock selection. This might get complicated unless you can use a single master clock.
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