Clock division and multiplexing in Cyclone-I

Have you considered using clock enable.

You run 100 and 160 clocks without PLL.

You design two clock domains one at 100 and the other at 160.

For any logic running at 1/2,1/4 or 1/8 of its clock speed you simply provide clock enable regulary pulsed every other clock(for 1/2), every 4th clock(for 1/4) and every 8th clock(for 1/8).

If you have to select only one rate among all above then run all on 160 and produce clock enable accordingly. for 100,100/2,100/4,100/8 you can use modulo adder to generate clock enable. I suggest the modulo adder running 0~319 counts as follows:

to get 100MHz: increment by 200

to get 50MHz: increment by 100

to get 25MHz:increment by 50

to get 12.5MHz:increment by 25

at overflow, generate one enable pulse. All you need is to get detect overflow correctly. but take care to add the increment carefully at this overflow.