Clock division and multiplexing in Cyclone-I

If you want to avoid timing problems I suggest you approach with a two perspectives: Fpga Internal processing & driving clock out.

For internal processing use clock enable as stated before. This is very simple to run on 160MHz then all you need is only change the increment value of your 320 modulo adder as illustrated below:

incr : 320 => 160MHz rate (or '1' always) = 160 320/320

incr : 160 => 80MHz rate = 160 x 160/320

incr : 80 => 40MHz rate = 160 x 80/320

incr : 40 => 20MHz rate = 160 x 40/320

incr : 200 => 100Mhz rate = 160 x 200/320

icrr : 100 => 50MHz rate = 160 x 100/320

incr : 50 => 25MHz rate = 160 x 50/320

incr : 25 => 12.5MHz rate = 160 x 25/320

For clocking out:

use your PLLs to generate the 8 clocks. use two PLLs, one for each clock input or use one pll if it can generate all 8 clocks. Then you can select out any clock you want. clock mux is not necessary for driving clock out. It is meant for internal use.

If you get io timing problems then consider using dc fifo to bridge data over, the safest way is to have 8 fifos each just few words deep.

each fifo is connected to its write clk and clk enable and its separate read clock from PLL then you only switch data out