clock divider

Have you tried the PLL thingy. That is one option, the other being a clock enable at a rate of 332/500 or 83/125 of the 50 MHz clock (modulo adder).

Thanks for your response!:)

You better use a modulo adder e.g. add 83 modulo 125 and generate clk en at overflow.

variable count : integer range 0 to 124 := 0;
process
begin
wait until clk50mhz = '1';
if count < 125 then
     count := count + 83;
     clken <= '0';
else
     count := count - 125;
     clken <= '1';
end if;
end process;

I second Kaz on this, with a minor modification. I have always used a modulo counter for clock division. So you can use a counter to count the cycles, thus increase it by one each cycle, and once a value is reached, set the clock high. In this way you won't need the adder and subtractor in Kaz's code (incrementor is cheaper in terms of HW).

I see what you mean. Thanks for the clarification.

However you can count 125 clocks then output 83 clocks withing each 125 as high enable. But I prefer to have it as spread as possible

I used the pll and I get my result. I think the alt-pll is very easy and more accurate.