Altera_Forum
Honored Contributor
Honored Contributorclock divider
Hi, how can I divide the 50 mhz clk to 33.2 mhz clk in vhdl code?
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Altera_ForumHonored Contributor
Honored ContributorHave you tried the PLL thingy. That is one option, the other being a clock enable at a rate of 332/500 or 83/125 of the 50 MHz clock (modulo adder).
Thus you bash your flips on 50MHz but slow them down at enable rate.
