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Altera_Forum
Honored Contributor
Honored Contributorclock divider
Hi, how can I divide the 50 mhz clk to 33.2 mhz clk in vhdl code?
Altera_ForumHonored Contributor
Honored ContributorHowever you can count 125 clocks then output 83 clocks withing each 125 as high enable. But I prefer to have it as spread as possible
