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Altera_Forum's avatar
Altera_Forum
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10 years ago

Clock constraints being ignored

I am working on a design on MAX V CPLD : 5M2210ZF324C5 on Quartus II 15.0 version.

I have a clock coming from one of the pins and I have create_clock constraint for this as shown below:

create_clock -name {Cpld_Clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {Cpld_Clk}]

However in the fitter report and sta report I get the following warnings:

Warning (332174): Ignored filter at 12g_main_hp_mlk_top.sdc(148): Cpld_Clk could not be matched with a port

Warning (332049): Ignored create_clock at 12g_main_hp_mlk_top.sdc(148): Argument <targets> is an empty collection

Info (332050): create_clock -name {Cpld_Clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {Cpld_Clk}]

Can anyone please tell me why the constraints have been ignored?

Thank you

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    'Cpld_Clk' isn't a top level port in your design.

    Do you have a signal called 'Cpld_Clk'? Is it being used as a clock? How is it generated?

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I think you also need a constraint specifying the pin it is connected to.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Looks fine. It is case sensitive by default, so maybe that's it?

    In TQ, go to View -> Name Finder, select get_ports and search on *. Does your port show up? If it does, keep fixing the wildcard until it matches just that one, although the reason will probably become apparent. If it doesn't show up, then I'm guessing this port was synthesized out of your design and it's an RTL/synthesis issue instead of a TimeQuest issue.