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Altera_Forum
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10 years ago

Clock constraints being ignored

I am working on a design on MAX V CPLD : 5M2210ZF324C5 on Quartus II 15.0 version. I have a clock coming from one of the pins and I have create_clock constraint for this as shown below: creat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Looks fine. It is case sensitive by default, so maybe that's it?

In TQ, go to View -> Name Finder, select get_ports and search on *. Does your port show up? If it does, keep fixing the wildcard until it matches just that one, although the reason will probably become apparent. If it doesn't show up, then I'm guessing this port was synthesized out of your design and it's an RTL/synthesis issue instead of a TimeQuest issue.