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Altera_Forum
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10 years ago

Clock constraints being ignored

I am working on a design on MAX V CPLD : 5M2210ZF324C5 on Quartus II 15.0 version. I have a clock coming from one of the pins and I have create_clock constraint for this as shown below: creat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

'Cpld_Clk' isn't a top level port in your design.

Do you have a signal called 'Cpld_Clk'? Is it being used as a clock? How is it generated?

Cheers,

Alex