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Altera_Forum's avatar
Altera_Forum
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18 years ago

Checking FPGA for LE damage

Hello,

We have a good reason to believe that an ACEX 1K FPGA on one of our board has some physical damage, i.e. some malfunctioning logic elements. Is there any standard way to test this ? I can think of two approaches:

1) Some ready solution provided by Altera for checking (say, by JTAG) that all of the FPGA's LEs are alive and functioning

2) Coding some special design that can clearly show that a problem exists

Your help is most appreciated

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    If you know which LEs may be damaged then a simple design can be used to toggle the LE and you can use SignalTap II to observe the results. Similarly you can create a shift register as large as the device (or break up in rows if you wish). Thirdly, you can file a service request at https://mysupport.altera.com/eservice/ and request an ERMA to be conducted for failure analysis for your device.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi there

    SignalTap is not supported by ACEX.

    Personally I don't think that only one LE is damaged - in this case the config probably would also fail in first place.

    It is also not possible to read back the config stream.

    Maybee you could fill in a large serial fifo....but I guess the best way is to desolder and mount a new one.

    regards

    Daniel
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    That's right. SignalTap is for later devices.

    Does the ACEX 1K with suspected LE damage still configure correctly?

    What makes you think there is damage? Have you ruled out a timing issue? Or logic hazard in the design?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I don't think that only one LE is damaged, I've never heared of such a case. If there is a damage, then more likely on the I/Os.

    For me it sounds more like an asynchronous design issue where from the outside you believe that the device is damaged because it produces strange behaviour - in fact there are only some internally produced glitches which let the logic switch randomly.

    He should look at the design to make sure it's synchronous, check timing analyses...

    regards

    Daniel
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Daniel, I agree with you mostly. It is possible but much less likely to have a die defect, however this should be caught by production flow testing prior to shipping the device.

    Eliben, I agree the liklihood is a design issue. Check your P's and Q's then if all checks out file an SR so Altera can help you evaluate further as needed.