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12 Replies
- Altera_Forum
Honored Contributor
BTTT
No one? - Altera_Forum
Honored Contributor
--- Quote Start --- Are the details of this integrity checking published? --- Quote End --- Nope. --- Quote Start --- I'd like to have a host processor test the bitstream image before trying to use it to configure my FPGA. I could wrap my own CRC around the image, but I'd rather not if I don't have to. --- Quote End --- I used U-Boot's mkimage to add a header and checksum. U-Boot can then test the integrity after flashing the image. Eg., see p29 http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf Cheers, Dave - Altera_Forum
Honored Contributor
Not published, bother (or words to that effect)
- Altera_Forum
Honored Contributor
--- Quote Start --- Not published, bother (or words to that effect) --- Quote End --- Not officially anyway ... I did come across this page ... http://www.pldtool.com/pld-file-formats But have not checked that the description of the .pof format is similar to the .sof format. Cheers, Dave - Altera_Forum
Honored Contributor
Greetings!
I have a similar problem, I use a host processor configuring a Cyclone II using PS configuration Scheme, and I don't use the INIT_DONE pin. I want to use the host processor to calculate FPGA's SRAM checksum after configuration and compare with the .RBF checksum sent by PC. So, there is my question, it's possible read Configuration SRAM data? - Altera_Forum
Honored Contributor
--- Quote Start --- it's possible read Configuration SRAM data? --- Quote End --- Nope. Cheers, Dave - Altera_Forum
Honored Contributor
Hi Dave! Thanks for the quick reply!
Well, I will find a way to validate the configuration. Maybe doing the FPGA return a clock signal when in user mode. - Altera_Forum
Honored Contributor
--- Quote Start --- Well, I will find a way to validate the configuration. Maybe doing the FPGA return a clock signal when in user mode. --- Quote End --- You validate configuration using the nSTATUS and CONF_DONE signals. The INIT_DONE signal simply indicates that the device is in USER mode. You don't need this signal if you do not want it. Did you look at the timing diagrams in the document I linked to above? Cheers, Dave - Altera_Forum
Honored Contributor
Hi, Dave!
Yes, I saw the diagram! And now I get it! If CONF_DONE rises there is no doubt that a valid configuration was sent. I think I messed a little! Thanks for the help! - Altera_Forum
Honored Contributor
--- Quote Start --- Yes, I saw the diagram! And now I get it! If CONF_DONE rises there is no doubt that a valid configuration was sent. I think I messed a little! --- Quote End --- Once CONF_DONE goes high, you may have to send some DCLK cycles to enter USER mode. The data sheet tells you how many. Sometimes the programming file ends with enough FFh values to implement the required clocks. This would only cause an issue while debugging your first board. Once you have that figured out, the fact that CONF_DONE asserts, and nSTATUS does not, is enough to let you know that the configuration was ok. Cheers, Dave