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Altera_Forum
Honored Contributor
Honored ContributorChecking configuration bitstream integrity (Cyclone IV)
I believe the configuration bitstream contains checksums or similar which the target FPGA checks for errors or corruption. Are the details of this integrity checking published? I'd like to have a hos...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Well, I will find a way to validate the configuration. Maybe doing the FPGA return a clock signal when in user mode. --- Quote End --- You validate configuration using the nSTATUS and CONF_DONE signals. The INIT_DONE signal simply indicates that the device is in USER mode. You don't need this signal if you do not want it. Did you look at the timing diagrams in the document I linked to above? Cheers, Dave
