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Altera_Forum's avatar
Altera_Forum
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12 years ago

Checking configuration bitstream integrity (Cyclone IV)

I believe the configuration bitstream contains checksums or similar which the target FPGA checks for errors or corruption. Are the details of this integrity checking published? I'd like to have a hos...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Yes, I saw the diagram! And now I get it!

If CONF_DONE rises there is no doubt that a valid configuration was sent. I think I messed a little!

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Once CONF_DONE goes high, you may have to send some DCLK cycles to enter USER mode. The data sheet tells you how many. Sometimes the programming file ends with enough FFh values to implement the required clocks. This would only cause an issue while debugging your first board. Once you have that figured out, the fact that CONF_DONE asserts, and nSTATUS does not, is enough to let you know that the configuration was ok.

Cheers,

Dave