Honored ContributorI want to change the clock frequency of FPGA DE0 board from 50MHZ to 8MHZ, As my IP core generally worked at 8MHZ. How can I realize this? Use PLL? If I use PLL, the input is the 50MHZ, how can I connect the output 8MHZ to the CPU core?
Honored ContributorYes, you can use a PLL.
Instantiate a PLL, connect the clk pin to the PLL input and the PLL output to the CPU's cllk signal.Honored ContributorThank you for your reply. If I donot want use pll, is there any other way to realise this? As I need to measure the power of FPGA core only, if use pll, it will increase the power of FPGA core right?
Honored ContributorAnd when I use PLL, the input name of clock is osc_clk, but in the pin assignment the name of clock is still the CPU's clk, it doesnot change,I donot why. It seems the pll doesn't work. Do you know where is wrong?
Honored ContributorYes, if you use a PLL the FPGA will draw a bit more power.
If you don't want to use the PLL, you have two options. Option one, use a ripple clock divider. Which will also draw a bit more power, but problably not as much as a PLL. Though, these can make timming closure harder. Option two, use an external 8 MHz clock source and feed it to the DE0 board. I don't see an external clock input in it but you might be able to use one of the generic inputs.
