Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYes, if you use a PLL the FPGA will draw a bit more power.
If you don't want to use the PLL, you have two options. Option one, use a ripple clock divider. Which will also draw a bit more power, but problably not as much as a PLL. Though, these can make timming closure harder. Option two, use an external 8 MHz clock source and feed it to the DE0 board. I don't see an external clock input in it but you might be able to use one of the generic inputs.