Honored ContributorHi there,
Is there a way to generate a phase locked 2MHz clock from a 2Mbps 8B10B data stream? All the CDRs I can find are made for higher bit rates. I thought it would be easier for lower bit rates. Xilinx has this solution: http://www.xilinx.com/support/documentation/application_notes/xapp868.pdf Does Altera have anything like this? Thanks, Hua
Honored ContributorIt's a basic all-digital PLL. Unlike a highspeed CDR circuit, it doesn't need special analog functions (e.g. an analog PLL), so it can be build with any FPGA. ADPLL design is a topic in standard PLL literature, e.g. Roland E. Best, phase-locked loops, design, simulation and application.
There's another option to use the PLL dynamic phase shift option present e.g. in Cyclone III FPGAs to build a software CDR. It can work up to 100 or 200 MBPS speed. But I'm not aware of an Altera reference design demonstrating this method..Honored ContributorHonored ContributorI think, it should. A classical all-digital PLL exposes a maximum timing jitter of one system clock period (e.g. 10 to 20 ns) which should be most likely sufficient for 2 MBPS. Utilizing the VCO dynamic phase shift option, the phase adjustment resolution is 1/8 PLL VCO period, respectively 125 - 250 ps. Other phase interpolation methods with at least 1 to 2 ns resolution can be used with other FPGA families.
Similar to many hardware CDRs, the VCO phase shift software CDR has a limited adjustment range of +/- several 100 ppm up to 1000 ppm around the reference frequency. Should be always sufficient with usual crystal clock accuracy.Honored ContributorHonored ContributorI don't know a literature. It's a possibility presented by the Cyclone III architecture. The term soft CDR is used in the Altera literature for a CDR function based on the DPA circuit of advanced FPGAs.
A simple soft CDR based on the VCO phase shift can work like this: You have a bitclock from the VCO sampling the input data stream. In locked state, the clock rising edge shall be aligned to the bit center. The bitstream is also sampled at the falling edge to check the phase. If the input state changes, you generate either an up or down pulse for the VCO depending on the detected bitstream's edge position. At lower input data rates, a higher oversampling ratio than 2 would give a more continuous phase information and suggest the usage of a loop filter. So you get closer to classical all-digital PLL.Honored ContributorDid you every get anywhere on this?
I am interested as I wish to do something similar using Cyclone IV E. Ian
