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Altera_Forum
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16 years ago

CDR Solution for 2Mbps 8B10B data stream

Hi there, Is there a way to generate a phase locked 2MHz clock from a 2Mbps 8B10B data stream? All the CDRs I can find are made for higher bit rates. I thought it would be easier for lower bit ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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There's another option to use the PLL dynamic phase shift option present e.g. in Cyclone III FPGAs to build a software CDR. It can work up to 100 or 200 MBPS speed. But I'm not aware of an Altera reference design demonstrating this method..

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Does the soft-CDR work at 2Mbps bit rate?

Thanks,

Hua