CDR Solution for 2Mbps 8B10B data stream

I don't know a literature. It's a possibility presented by the Cyclone III architecture. The term soft CDR is used in the Altera literature for a CDR function based on the DPA circuit of advanced FPGAs.

A simple soft CDR based on the VCO phase shift can work like this:

You have a bitclock from the VCO sampling the input data stream. In locked state, the clock rising edge shall be aligned to the bit center. The bitstream is also sampled at the falling edge to check the phase. If the input state changes, you generate either an up or down pulse for the VCO depending on the detected bitstream's edge position.

At lower input data rates, a higher oversampling ratio than 2 would give a more continuous phase information and suggest the usage of a loop filter. So you get closer to classical all-digital PLL.