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Honored Contributor
Honored ContributorCDR Solution for 2Mbps 8B10B data stream
Hi there, Is there a way to generate a phase locked 2MHz clock from a 2Mbps 8B10B data stream? All the CDRs I can find are made for higher bit rates. I thought it would be easier for lower bit ...
Altera_ForumHonored Contributor
Honored ContributorI think, it should. A classical all-digital PLL exposes a maximum timing jitter of one system clock period (e.g. 10 to 20 ns) which should be most likely sufficient for 2 MBPS. Utilizing the VCO dynamic phase shift option, the phase adjustment resolution is 1/8 PLL VCO period, respectively 125 - 250 ps. Other phase interpolation methods with at least 1 to 2 ns resolution can be used with other FPGA families.
Similar to many hardware CDRs, the VCO phase shift software CDR has a limited adjustment range of +/- several 100 ppm up to 1000 ppm around the reference frequency. Should be always sufficient with usual crystal clock accuracy.
