CDR Solution for 2Mbps 8B10B data stream

It's a basic all-digital PLL. Unlike a highspeed CDR circuit, it doesn't need special analog functions (e.g. an analog PLL), so it can be build with any FPGA. ADPLL design is a topic in standard PLL literature, e.g. Roland E. Best, phase-locked loops, design, simulation and application.

There's another option to use the PLL dynamic phase shift option present e.g. in Cyclone III FPGAs to build a software CDR. It can work up to 100 or 200 MBPS speed. But I'm not aware of an Altera reference design demonstrating this method..