Hello, I use Quartus Prime Lite Edition with Questa Intel FPGA Starter edition ver. 21.1 on a Win 11 PC, and I have a DE10-Lite board. I followed an old, short tutorial to simulate the Altera Modular ADC IP: https://www.youtube.com/watch?v=6UscboZ1Vho I compiled the IP (.qip file), included the .sip file, attached the testbench and run the simulation. Questa simulation starts, but stops during the optimization: # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L altera_trace_adc_monitor_wa_inst -L timing_adapter_1 -L timing_adapter_0 -L data_format_adapter_0 -L rst_controller -L trace_endpoint -L core -L avalon_st_adapter_001 -L avalon_st_adapter -L st_splitter_internal -L adc_monitor_internal -L control_internal -L modular_adc_0 -voptargs=""+acc"" tb_adctest # Start time: 17:49:18 on Aug 12,2022# ** Note: (vsim-3812) Design is being optimized...# ** Error: E:/.../adcsimwoutf/simulation/submodules/adcsimwoutf_modular_adc_0_adc_monitor_internal.v(101): Module 'adcsimwoutf_modular_adc_0_adc_monitor_internal_core' is not defined.# For instance 'core' at path 'tb_adctest.u0.modular_adc_0.adc_monitor_internal'# ** Error: E:/.../adcsimwoutf/simulation/submodules/adcsimwoutf_modular_adc_0_adc_monitor_internal.v(121): Module 'adcsimwoutf_modular_adc_0_adc_monitor_internal_trace_endpoint' is not defined.# For instance 'trace_endpoint' at path 'tb_adctest.u0.modular_adc_0.adc_monitor_internal'# Optimization failed Can you post a new tutorial to perform ADC simulation with output file similar to the 2018 one, but more detailed and working for newer Quartus and IP versions (in particular showing the compilation of all required blocks and a more detailed testbench, the one shown in the tutorial is completely missing pll clock)? Thanks in advance, Roberto.

Hello, Do you have the test case so I can replicate at my side? this will speed up the debugging work. regards,Farabi

Hello, Please refer to this link : https://www.intel.com/programmable/technical-pdfs/683596.pdfchapter 2.5 to refer to design simulation example. regards,Farabi

Hello Farabi, I explained myself not clearly. Chapter 2.5 of the document you suggest doesn't add anything new to the tutorial described in https://www.youtube.com/watch?v=6UscboZ1Vho My problem is with the ADC simulation IP Core generated automatically by Quartus. Questa is not able to simulate the ADC IP core, and I don't know why. Probably I need to check https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html#mwh1409960615330 9. Third-party Simulation However, it seems to me very strange that is not provided an updated tutorial video about the simulation of the Altera Modular ADC IP, with details about ADC simulation model and testbench generation and compilation. My humble suggestion is to provide a new, more detailed version, of the video tutorial about ADC IP simulation. If I will be able to simulate it in the future I'll do it for you ;-).

Hello, I would like to update this post because I can now run the simulation of the modular ADC IP core (control core only), but it doesn't work because of some problems in the simulation ADC model. This is the warning obtained at the end of the test bench compilation: # ** Note: (vsim-3812) Design is being optimized...# ** Warning: E:/IntelFPGA/DE10-Lite_ADC/SimProjects/PRG4/adc2sim/simulation/submodules/adc2sim_modular_adc_0.vhd(60): (vopt-3473) Component instance "control_internal : adc2sim_modular_adc_0_control_internal" is not bound.# Region: /ADCsim_top_vhd_tst/inst1/modular_adc_0# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1. # Loading modular_adc_0.adc2sim_modular_adc_0(rtl)#1# ** Warning: (vsim-3473) Component instance "control_internal : adc2sim_modular_adc_0_control_internal" is not bound.# Time: 0 ps Iteration: 0 Instance: /adcsim_top_vhd_tst/inst1/modular_adc_0 File: E:/IntelFPGA/DE10-Lite_ADC/SimProjects/PRG4/adc2sim/simulation/submodules/adc2sim_modular_adc_0.vhd# Loading work.adcfsm(adcfsm_arch)#1# ** Warning: (vsim-8684) No drivers exist on out port /adcsim_top_vhd_tst/inst1/modular_adc_0/command_ready, and its initial value is not used.# Therefore, simulation behavior may occur that is not in compliance with# the VHDL standard as the initial values come from the base signal /adcsim_top_vhd_tst/comm_r. In fact, the IP tool generated submodule adc2sim_modular_adc_0.vhd instantiates a component adc2sim_modular_adc_0_control_internal that is not present in the other submodules. The only component present is altera_modular_adc_control. So adc2sim_modular_adc_0_control_internal doesn't exist and is not bounded: all ADC signals are X as shown in the simulation. Am I skipping some passage? Thank you for any help on the subject. I use Quartus Prime Lite Edition with Questa Intel FPGA Starter edition ver. 21.1 on a Win 11 PC, and I have a DE10-Lite board. I have been able to synthesize the project and see it working on the board using the ADC output to drive the 7 seg displays, but I can't simulate it with Questa.

Hello, thank you very much Farabi for your support. Here attached is the project whose simulation starts but doesn't work. README.txt explains the object of the project. Modular ADC Intel FPGA IP hdl simulation files are generated selecting VHDL. The main folder contains some pictures with the screenshot of the ADC IP parameter settings. I also tried to generate Modular ADC Intel FPGA IP hdl simulation files in Verilog: in this case the simulation doesn't work because of some parameters that do not match between ADC description and verilog hdl simulation file. Thanks for your support. Regards, Roberto.

Can't simulate ADC as shown in the tutorial

20 Replies

Farabi_Altera
Regular Contributor
3 years ago
Hello,

Do you have the test case so I can replicate at my side? this will speed up the debugging work.

regards,
Farabi
- Roberto07
  New Contributor
  3 years ago
  Hello,
  
  thank you very much Farabi for your support.
  
  Here attached is the project whose simulation starts but doesn't work.
  
  README.txt explains the object of the project.
  
  Modular ADC Intel FPGA IP hdl simulation files are generated selecting VHDL. The main folder contains some pictures with the screenshot of the ADC IP parameter settings.
  
  I also tried to generate Modular ADC Intel FPGA IP hdl simulation files in Verilog: in this case the simulation doesn't work because of some parameters that do not match between ADC description and verilog hdl simulation file.
  
  Thanks for your support.
  
  Regards,
  
  Roberto.
  vhdlsimnotok.zip7.6 MB
Farabi_Altera
Regular Contributor
3 years ago
Hello,

Please refer to this link : https://www.intel.com/programmable/technical-pdfs/683596.pdf
chapter 2.5 to refer to design simulation example.

regards,
Farabi
Roberto07
New Contributor
3 years ago
Hello Farabi,

I explained myself not clearly.

Chapter 2.5 of the document you suggest doesn't add anything new to the tutorial described in https://www.youtube.com/watch?v=6UscboZ1Vho

My problem is with the ADC simulation IP Core generated automatically by Quartus. Questa is not able to simulate the ADC IP core, and I don't know why. Probably I need to check https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html#mwh1409960615330

9. Third-party Simulation

However, it seems to me very strange that is not provided an updated tutorial video about the simulation of the Altera Modular ADC IP, with details about ADC simulation model and testbench generation and compilation.

My humble suggestion is to provide a new, more detailed version, of the video tutorial about ADC IP simulation.

If I will be able to simulate it in the future I'll do it for you ;-).
Roberto07
New Contributor
3 years ago
Hello,

I would like to update this post because I can now run the simulation of the modular ADC IP core (control core only), but it doesn't work because of some problems in the simulation ADC model.

This is the warning obtained at the end of the test bench compilation:

# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: E:/IntelFPGA/DE10-Lite_ADC/SimProjects/PRG4/adc2sim/simulation/submodules/adc2sim_modular_adc_0.vhd(60): (vopt-3473) Component instance "control_internal : adc2sim_modular_adc_0_control_internal" is not bound.
# Region: /ADCsim_top_vhd_tst/inst1/modular_adc_0
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.

# Loading modular_adc_0.adc2sim_modular_adc_0(rtl)#1
# ** Warning: (vsim-3473) Component instance "control_internal : adc2sim_modular_adc_0_control_internal" is not bound.
# Time: 0 ps Iteration: 0 Instance: /adcsim_top_vhd_tst/inst1/modular_adc_0 File: E:/IntelFPGA/DE10-Lite_ADC/SimProjects/PRG4/adc2sim/simulation/submodules/adc2sim_modular_adc_0.vhd
# Loading work.adcfsm(adcfsm_arch)#1
# ** Warning: (vsim-8684) No drivers exist on out port /adcsim_top_vhd_tst/inst1/modular_adc_0/command_ready, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /adcsim_top_vhd_tst/comm_r.

In fact, the IP tool generated submodule adc2sim_modular_adc_0.vhd instantiates a component adc2sim_modular_adc_0_control_internal that is not present in the other submodules. The only component present is altera_modular_adc_control. So adc2sim_modular_adc_0_control_internal doesn't exist and is not bounded: all ADC signals are X as shown in the simulation.

Am I skipping some passage?

Thank you for any help on the subject.

I use Quartus Prime Lite Edition with Questa Intel FPGA Starter edition ver. 21.1 on a Win 11 PC, and I have a DE10-Lite board. I have been able to synthesize the project and see it working on the board using the ADC output to drive the 7 seg displays, but I can't simulate it with Questa.
Roberto07
New Contributor
3 years ago
Hello,

thank you very much Farabi for your support.

Here attached is the project whose simulation starts but doesn't work.

README.txt explains the object of the project.

Modular ADC Intel FPGA IP hdl simulation files are generated selecting VHDL. The main folder contains some pictures with the screenshot of the ADC IP parameter settings.

I also tried to generate Modular ADC Intel FPGA IP hdl simulation files in Verilog: in this case the simulation doesn't work because of some parameters that do not match between ADC description and verilog hdl simulation file.

Thanks for your support.

Regards,

Roberto.
vhdlsimnotok.zip7.6 MB
Roberto07
New Contributor
3 years ago
Hello Farabi,

any news about Modular ADC Intel FPGA IP hdl simulation model? How long will it take to have a new working hdl simulation model?

Thank you for the update.

Regards,

Roberto.
FakhrulA_altera
Regular Contributor
3 years ago
Hi Roberto,

Understood. I am checking this internally for more clarification
Will get to you once there is any findings.

Thanks!
FakhrulA_altera
Regular Contributor
3 years ago
Hi Roberto,

Could you please give a try with the following example and see what is the outcome:

MAX 10 - ADC example

Thank you.
FakhrulA_altera
Regular Contributor
3 years ago
Hi Roberto,

I wish to follow up with you about this case. Do you have any further questions on this matter? Please feel free to let me know if there is any concern so that we could further assist you.

Otherwise, this thread will be marked as inactive and will be transitioned to community support because there is no update received from you in a while.

Regards,
Fakhrul
Roberto07
New Contributor
3 years ago
Hi Fakhrul,

thank you for your support but this is not what I'm looking for.