Can't simulate ADC as shown in the tutorial

Hello,

thank you very much Farabi for your support.

Here attached is the project whose simulation starts but doesn't work.

README.txt explains the object of the project.

Modular ADC Intel FPGA IP hdl simulation files are generated selecting VHDL. The main folder contains some pictures with the screenshot of the ADC IP parameter settings.

I also tried to generate Modular ADC Intel FPGA IP hdl simulation files in Verilog: in this case the simulation doesn't work because of some parameters that do not match between ADC description and verilog hdl simulation file.

Thanks for your support.

Regards,

Roberto.