The purpose of the project is to be able to reproduce/simulate with Questa the
ADC waveforms as shown in Fig. ADCwaves.png.
The project contains two IP blocks:
- the PLL1 to drive the ADC pll clocks
- the ADC1, Modular ADC core Intel FPGA IP
The IP tool is used to generate the hdl files. For the Modular ADC core Intel FPGA IP two
different hdl description files are generated, one for synthesis and one for simulation. 
Moreover the project contains a simple custom FSM to synchronize external command signals 
with the system clock. This FSM is simplified and does not manage handshake with the ADC:
however it should be able to at least start the conversion, that is the purpose of this
simplified project.
A more complex project (with a custom timer to set up the acquisition time and a custom FSM
to drive the ADC that supports handshake too) has been synthesized and works correctly on DE10-Lite board.
However, it can't be simulated.
the simplified project for simulation, that don't work, is attached:
- vhdlsim.zip

