Can't simulate ADC as shown in the tutorial

Hello,

I would like to update this post because I can now run the simulation of the modular ADC IP core (control core only), but it doesn't work because of some problems in the simulation ADC model.

This is the warning obtained at the end of the test bench compilation:

# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: E:/IntelFPGA/DE10-Lite_ADC/SimProjects/PRG4/adc2sim/simulation/submodules/adc2sim_modular_adc_0.vhd(60): (vopt-3473) Component instance "control_internal : adc2sim_modular_adc_0_control_internal" is not bound.
# Region: /ADCsim_top_vhd_tst/inst1/modular_adc_0
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.

# Loading modular_adc_0.adc2sim_modular_adc_0(rtl)#1
# ** Warning: (vsim-3473) Component instance "control_internal : adc2sim_modular_adc_0_control_internal" is not bound.
# Time: 0 ps Iteration: 0 Instance: /adcsim_top_vhd_tst/inst1/modular_adc_0 File: E:/IntelFPGA/DE10-Lite_ADC/SimProjects/PRG4/adc2sim/simulation/submodules/adc2sim_modular_adc_0.vhd
# Loading work.adcfsm(adcfsm_arch)#1
# ** Warning: (vsim-8684) No drivers exist on out port /adcsim_top_vhd_tst/inst1/modular_adc_0/command_ready, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /adcsim_top_vhd_tst/comm_r.

In fact, the IP tool generated submodule adc2sim_modular_adc_0.vhd instantiates a component adc2sim_modular_adc_0_control_internal that is not present in the other submodules. The only component present is altera_modular_adc_control. So adc2sim_modular_adc_0_control_internal doesn't exist and is not bounded: all ADC signals are X as shown in the simulation.

Am I skipping some passage?

Thank you for any help on the subject.

I use Quartus Prime Lite Edition with Questa Intel FPGA Starter edition ver. 21.1 on a Win 11 PC, and I have a DE10-Lite board. I have been able to synthesize the project and see it working on the board using the ADC output to drive the 7 seg displays, but I can't simulate it with Questa.