can the pll locked signal of the max10 be used as the reset signal ?

Question

engwei_o_intel · Answer

Hi Zhang Lan
In general, we don't want to use the PLL lock signal as the reset signal directly. The reset will be an asynchronous reset and some of the PLL lock signals may toggle for a while before they stay in a static state. You must ensure that the asynchronous reset is debounced and filtered. You can refer to Asynchronous Reset section in the link below:
https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51006.pdf

thanks.
Eng Wei

zlan01 · Answer

Thanks for your help,
and the information mentioned in the figure below  applys to  max10 or not ?

zlan01 · Answer

and there are no INIT_DOWN and nINIT_DOWN signal, is there any other signal can be used as the init done signal for the max10 ?

zlan01 · Answer

that is I want to implement the similar reset circuit shown in the above figue in page 5 of AN 891, can I ?

engwei_o_intel · Answer

Hi Zhang Lan

Nope, this pin isn't available for Max10. Designers typically use an explicit reset signal for the design, which forces all registers into their appropriate values after reset. Intel recommends this practice to reset the device after power-up to restore the proper state.

thanks.
Eng Wei

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can the pll locked signal of the max10 be used as the reset signal ?

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