Forum Discussion
EngWei_O_Intel
Frequent Contributor
5 years agoHi Zhang Lan
In general, we don't want to use the PLL lock signal as the reset signal directly. The reset will be an asynchronous reset and some of the PLL lock signals may toggle for a while before they stay in a static state. You must ensure that the asynchronous reset is debounced and filtered. You can refer to Asynchronous Reset section in the link below:
https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51006.pdf
thanks.
Eng Wei
- zlan015 years ago
New Contributor
Thanks for your help,
and the information mentioned in the figure below applys to max10 or not ?