can not verify DDR SDRAM write activity using SignalTap

found some problems.

Even before I input write address in Nios, haven't run the IORW function yet, there are already a lot of local_write_req pulses available and captured by SignalTap. I don't understand, where are these write/read request from? my Nios II program is still waiting for address to do IORW. Why there are already read request and write request?

Any one has similar problems?

Thank you very much!

Well, I imagine there's a lot more to your code than just the IOWR command. The processor starts fetching code at the Reset Address. Generate an objdump file and take a look at everything all the code that exists prior to your IOWR command.

Additionally, if you're using an "f" core, you likely have data/instruction cache and branch prediction, which means that the processor could be fetching instructions just to fill a cache line.

Cheers,

-slacker

Will the fetching code affects "local_write_req" and "local_read_req"?

There is almost no any codes related to DDR SDRAM before IOWR:

as shown below:

# include<stdio.h># include"sys/alt_dma.h"# include "sys/alt_cache.h"# include "system.h"# include "altera_avalon_dma_regs.h"# define length 512

int to_hex(char* pkt)

{

unsigned int value[8];

unsigned int value1=0;

unsigned int q;

for (q=0;q<=7;q++)

{

value[q]=(pkt[q]>0x39)?(pkt[q]-0x37):(pkt[q]-0x30);

if (q==0)

{

value1=(value1+value[q]);

}

else

{

value1=((value1<<4)+value[q]);

}

}

return value1;

}

void Single_Write(void)

{

unsigned char write_offset[8];

unsigned char data[8];

unsigned int DDR_write_OFFSET_ADDRESS;

unsigned int write_data;

printf(" \n Single Write operation \n");

printf( "\n Enter the data you want to write to the Memory:(i.e.44444444) \n");

gets(data);

write_data=to_hex(&data[0]);

printf( "\n Enter the offset address where you want to write in the Memory: (i.e. 00000010)\n");

gets(write_offset);

DDR_write_OFFSET_ADDRESS = to_hex(&write_offset[0]);

if

((DDR_write_OFFSET_ADDRESS<0)||(DDR_write_OFFSET_ADDRESS>=(ALTMEMDDR_SPAN/4)))

{

printf(" \n Invalid Offset \n");

printf( "\n You have entered wrong offset address : \n");

return;

}

IOWR(ALTMEMDDR_BASE,DDR_write_OFFSET_ADDRESS,write_data);

if (IORD(ALTMEMDDR_BASE,DDR_write_OFFSET_ADDRESS)==write_data)

{

printf("\n Data: %08x is correctly written to memory offset: %08x\n", write_data,DDR_write_OFFSET_ADDRESS);

printf("\n Write operation is done \n");

}

else

{

printf("\n Write operation is Failed \n");

}

}

int main()

{

Single_Write();

return 0 ;

}

--- Quote Start ---

Well, I imagine there's a lot more to your code than just the IOWR command. The processor starts fetching code at the Reset Address. Generate an objdump file and take a look at everything all the code that exists prior to your IOWR command.

Additionally, if you're using an "f" core, you likely have data/instruction cache and branch prediction, which means that the processor could be fetching instructions just to fill a cache line.

Cheers,

-slacker

--- Quote End ---

The same problem happens again and again? do I have anything wrong with signalTap? Even before I input write address in Nios, haven't run the IORW function yet, there are already a lot of local_write_req pulses available and captured by SignalTap.

Anyone have successful experience?