can not verify DDR SDRAM write activity using SignalTap

Well, I imagine there's a lot more to your code than just the IOWR command. The processor starts fetching code at the Reset Address. Generate an objdump file and take a look at everything all the code that exists prior to your IOWR command.

Additionally, if you're using an "f" core, you likely have data/instruction cache and branch prediction, which means that the processor could be fetching instructions just to fill a cache line.

Cheers,

-slacker