Honored ContributorThe clock in my project is transmitting by LVDS.
Can I use ALTPLL in Cyclone II in this way : I connect clk+ to LVDSCLK0p, clk- to LVDSCLK0n, then I use a ALTPLL in my design, its output c0 connect to PLL1_OUT. Is this right? I think, the IO bank where LVDSCLK0p and PLL1_OUT in is the same one, can I use a LVDS clock (in) and a normal clock (out) in this way . thank you.
Honored ContributorYes, it's correct.
Honored ContributorHonored ContributorYes, there's a special feature of the differential clock inputs according to this support solution:
http://www.altera.com/support/kdb/solutions/rd02132007_822.htmlHonored Contributoro! thanks a lot. I got it. This information is so useful!
--- Quote Start --- When Cyclone II dedicated clock input pins are configured for the LVDS or LVPECL I/O standard for input operations, the differential buffer is powered by VCCINT, not VCCIO. Thus, the VCCIO does not have to be 2.5V when you use LVDS or LVPECL I/O standards on the dedicated clock input pins for input operations. --- Quote End ---
