Can I exchange the positive signal (p) and negative (n) signal of LVDS?

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Is the LVDS clock signal can also be inverted inside the FPGA?

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You have to apply a phase shift. In my opinion, inverting the signals is good to fix layout errors, but I won't use it as regular design means.

Thanks for your help.

Is the LVDS clock signal can also be inverted inside the FPGA?

Yes.

Of course, you need to negate the signal inside your design.

Important notice: you can't put the inversion between a DDRIO (or ALTLVDS primitive, which uses DDRIO) and the pin.

So, if you're planing to use DDRIO or ALTLVDS, beware of that inversion.