Browse the ram content

It sounds like you are trying to make CAM - content addressable ram. This is not easy in an FPGA.

The adresses are not incremented like this, actually they are ouputs from another block so it's like that they are random adresses. I can't tell when they are generated neither their value.

Yes i know this circuit is implemented in logic but i thought this the only way i can check the ram content. Is there a possible way to browse ram content and get multiple adresses as output without using a for loop? knowing that it's not necessary to get all this adresses in just one clock cycle.

This code will not work in an FPGA. You can only access a single ram element per clock cycle. So this design will be implemented in logic.

Actually i'm doing this project using VHDL as a description language. Here's my code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.math_real.all;
library std;
entity active_tag is
    generic 
    (
        DATA_WIDTH : natural 
    );
    port 
    (    
        clk        : in std_logic;
        addr_a    : in std_logic_vector(2 downto 0);
        addr_b    : in std_logic_vector(2 downto 0);
        data_a    : in integer;
        we_a,rd_en    : in std_logic := '1';
        we_b    : in std_logic := '1';
        q : out integer;
        q_a        : out std_logic_vector(DatA_WIDTH-1 downto 0);
        q_b        : out std_logic_vector(Data_WIDTH-1 downto 0)
    );
end active_tag;
architecture rtl of active_tag is
    signal data1: std_logic_vector((DATA_WIDTH-1) downto 0);
    signal  add_a,add_b : integer range 0 to 7;
    -- Build a 2-D array type for the RAM
    subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
    type memory_t is array(7 downto 0) of word_t;
    -- Declare the RAM 
    shared variable ram : memory_t;
begin
add_a<=to_integer(unsigned(addr_a));
data1<=std_logic_vector(to_unsigned(data_a,data1'length));
    -- Port A
    process(clk)
    variable i : integer:=1 ;
    begin
    if(rising_edge(clk)) then
        if(we_a = '1') then
            ram(add_a) := data1;
        end if;
        if rd_en='1' then
            for add_a in 0 to 7 loop
                if (ram(add_a)=(y-1 mod 3)) then
                    q_a<=std_logic_vector(to_unsigned(add_a,q_a'length));
                    
                end if;
            end loop;
        end if;
    end if;
    end process;
    -- Port B 
    process(clk)
    begin
    if(rising_edge(clk)) then 
        if(we_b = '1') then
            ram(add_b) := "000";
            q_b <= addr_b;
        end if;
    end if;
    end process;
end rtl;

this is a little vague? is this is a software or HDL problem? why not post a code example?