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Altera_Forum
Honored Contributor
Honored ContributorBrowse the ram content
Hello everyone, i am doing image processing on fgpa. Actually i want to browse the ram content for every row of the image, and whenever the content of the adress is not updated i need to register...
Altera_ForumHonored Contributor
Honored ContributorThis code will not work in an FPGA. You can only access a single ram element per clock cycle. So this design will be implemented in logic.
Using a loop the way you have is NOT good practice. For example, here, if two addresses are a match, then it is the last one that will output to q_a. Do you know what circuit you expect from this code? have you got a diagram of it?
