Browse the ram content

It sounds like you are trying to make CAM - content addressable ram. This is not easy in an FPGA.

Also, your code looks like software rather than hardware. for loops in HDL are unrolled to make parallel or sequential logic. In your case, it is create 8 comparators and a 8-1 mux to select the correct ram register (because it is not a ram, its a load of registers) to use.

because you are muxing 8-1, comparing then muxing the result again in a single clock cycle, your Fmax is going to be very slow.