Honored ContributorHi,
I am using Cyclone II to generate a 5MHz clock pulse out from its IO pin and I am seeing ringing problem during the level transition. The overshoot and undershoot could more that 1V on LVTTL IO. Any clues to reduce the ringing problem? Thanks Phuah
Honored ContributorReduce the drive strength. Also make sure you are measuring at the destination end of the net.
Series termination at the source helps as does having a point to point connection.Honored ContributorAs a general remark, the ringing isn't specific to FPGA, it occurs with any fast digital logic. The advantage with FPGA is that you have means to control it in part as the said drive strength setting. Setting all FPGA outputs to minimum drive strength isn't a bad idea.
But you didn't tell about your measurement setup. It could be, that the ringing is present at your oscilloscope probe only, but not at the circuit. If you observe the ringing directly at the output pin, this may be the case. When you measure the signal at a distant load, the overshoot is likely to exist actually in the circuit. If minimum drive strength can't remove it, an additional series termination at the FPGA output may help. I assume that you have a low impedance common ground, typically a ground plane. If not, overshoot problems can be severe.Honored ContributorThanks for advices. The ringing issue on output pin was reduced to mininum when I set the drive strength to 4mA (degault setting is 24mA).
Honored ContributorAs FvM and I stated, look at the signal it the input end of the net, not the output of the FPGA. It's the input end that is "seeing" the signal.
Also for signal integrity measurements, a good high impedence, low capacitance scope probe should be use to see what is actually happening on the net.
