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Altera_Forum
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18 years ago

Boucing/Ringing seeing on Output pin of Cyclone II FPGA

Hi, I am using Cyclone II to generate a 5MHz clock pulse out from its IO pin and I am seeing ringing problem during the level transition. The overshoot and undershoot could more that 1V on LVTT...
Altera_Forum's avatar
Altera_Forum
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18 years ago

As FvM and I stated, look at the signal it the input end of the net, not the output of the FPGA. It's the input end that is "seeing" the signal.

Also for signal integrity measurements, a good high impedence, low capacitance scope probe should be use to see what is actually happening on the net.