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Altera_Forum
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18 years ago

Boucing/Ringing seeing on Output pin of Cyclone II FPGA

Hi, I am using Cyclone II to generate a 5MHz clock pulse out from its IO pin and I am seeing ringing problem during the level transition. The overshoot and undershoot could more that 1V on LVTT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for advices. The ringing issue on output pin was reduced to mininum when I set the drive strength to 4mA (degault setting is 24mA).