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Altera_Forum
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18 years ago

Boucing/Ringing seeing on Output pin of Cyclone II FPGA

Hi, I am using Cyclone II to generate a 5MHz clock pulse out from its IO pin and I am seeing ringing problem during the level transition. The overshoot and undershoot could more that 1V on LVTT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Reduce the drive strength. Also make sure you are measuring at the destination end of the net.

Series termination at the source helps as does having a point to point connection.

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