New ContributorBlock Memory Pipeline Controls
Have an old design in a Cyclone V, and recently added a 2-port, single-clock block memory; the read side is used to stuff words into an Avalon-mm interface. So to accommodate wait states, and overcome the read latency of the memory (two clocks, one for input address, one for output data), I implemented both the rd_addressstall and rden pipeline controls. But, the rden seems to have no effect at all on the behavior of the read data port. I worked around it by omitting the dead data register from the block memory macro and simply adding a register external to the read data port, enabled by the same signal that was driving rden.
That works as intended and all is well; but I am curious about the intention of the rden control. How should it work?
Thanks.
