Forum Discussion
waxwing
New Contributor
2 years agoBlock Memory Pipeline Controls
Have an old design in a Cyclone V, and recently added a 2-port, single-clock block memory; the read side is used to stuff words into an Avalon-mm interface. So to accommodate wait states, and overco...
RichardT_altera
Super Contributor
1 year agoYou may checkout this user guide on how the rden signal works.
https://www.intel.com/content/www/us/en/docs/programmable/683240/17-0/read-enable.html
https://www.intel.com/content/www/us/en/docs/programmable/683375/current/embedded-memory-modes.html
Regards,
Richard Tan