Blackjack using VHDL code

Question

My partner and I have an assignment to replicate a blackjack game using VHDL coding techniques on Quartus Max+II. We were to do this by using a Finite State Machine.

We are having trouble understanding how the 'process' and 'case' operations work. For example, do "When" statements (for our example, to switch the states of the FSM) in a 'case' operation, loop back upon themselves if you change states not in sequential order??? Or does the case statement just run through sequentially without redoing any WHEN statements when the "state" is changed.

ANY help is appreciated, even if it is just to explain how the 'case' and 'process' operations work, especially with the rising edge of the clock signal. THANK YOU VERY MUCH!!

our code is attached via word 2009....

The main problem we are having is that we cannot get certain scenarios to work correctly such as we cannot get the program to "bust" by having a bust output of 1 for any combination of numbers.

Some problems might include the general misunderstanding of how to write VHDL code AND also, we try to set certain states throughout the program as if the program will loop up to the correct WHEN statement when the corresponding state is called.

altera_forum · Answer

Typically a process gets executed once every clock cycle.

And a process can have case statements inside it. That's how you typically implement FSM's.

So you basically need one or more processes with case statements inside them.

You can have the when statements outside of a process, (concurent statements) but I do not recommend it.

altera_forum · Answer

on each clock tick, it will chose the appropriate "when" output of the case statement, depending on the current state. It then sets the next state depending on the inputs and current state. It does not loop - only 1 "when" output is selected per clock tick.

A process in VHDL describes a section of sequential VHDL. Any process will only be triggered when a change occurs to any of the signals in the sensitivity list. SO in your case (and the case for most processes) it is only triggered when the clock or reset signals change. A process basically describes anything thats happeneing in the VHDL.

altera_forum · Answer

--- Quote Start ---   You can have the when statements outside of a process, (concurent statements) but I do not recommend it.  --- Quote End ---    I highly recommend it if you know how to use it:  
my_output &lt;= A when select = '1' else B; --generate a mux

altera_forum · Answer

Tricky:

I find it easier (especially for students) if both state transitions and outputs are kept together inside the processes.

It will also generate muxes, with the advantage that they will be registered.

But yes, I am aware you can do state transitions inside a clocked process, and outputs in a combinatorial process or in a concurrent statement (basically outside of a clocked process).

I just recommended the other style due to my experience as a VHDL lab assistant at the University.

altera_forum · Answer

First of all thank you both very much for your time and effort, and this really did help me to understand the basics of how to implement a FSM using VHDL.

My design basically uses one process, and one HUGE case statement inside that process. Inside of the case statement I have about twenty when statements. The when statement that you see here seems to be where I am having the problems.

Is this a valid When statement?? And if so, will it go through the entire statement in one clock cycle??

Thanks again!!!

WHEN hitadd =>

IF (cardA <= "00001") THEN

state <= error2;

ELSIF (cardA > "01011") THEN

state <= error2;

END IF;

output <= (output + cardA);

charlie <= (charlie + 1);

hit <= '0';

IF (cardA = "01011") THEN

state <= aceadd;

ELSIF (output >= "10001") THEN

state <= decision;

ELSIF (output < "10001") THEN

state <= cchar;

END IF;

Forum Discussion

Blackjack using VHDL code

7 Replies

Recent Discussions

Agilex5 Engineering Silicon

Max10 Security Bit

Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?

MAX 10. No 3.0 V Schmitt Trigger I/O standard

Agilex Reset_Release no associated clock