Blackjack using VHDL code

First of all thank you both very much for your time and effort, and this really did help me to understand the basics of how to implement a FSM using VHDL.

My design basically uses one process, and one HUGE case statement inside that process. Inside of the case statement I have about twenty when statements. The when statement that you see here seems to be where I am having the problems.

Is this a valid When statement?? And if so, will it go through the entire statement in one clock cycle??

Thanks again!!!

WHEN hitadd =>

IF (cardA <= "00001") THEN

state <= error2;

ELSIF (cardA > "01011") THEN

state <= error2;

END IF;

output <= (output + cardA);

charlie <= (charlie + 1);

hit <= '0';

IF (cardA = "01011") THEN

state <= aceadd;

ELSIF (output >= "10001") THEN

state <= decision;

ELSIF (output < "10001") THEN

state <= cchar;

END IF;