Blackjack using VHDL code

on each clock tick, it will chose the appropriate "when" output of the case statement, depending on the current state. It then sets the next state depending on the inputs and current state. It does not loop - only 1 "when" output is selected per clock tick.

A process in VHDL describes a section of sequential VHDL. Any process will only be triggered when a change occurs to any of the signals in the sensitivity list. SO in your case (and the case for most processes) it is only triggered when the clock or reset signals change. A process basically describes anything thats happeneing in the VHDL.