Binary to Binary coded deicmal help

Hi guys,

I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input.

However, it seems like the binary goes through unchanged! Which I assume means +3 never happens... But why? Any ideas?

Thanks in advance, the code I've got so far is below.

module bcd(binary, bcd);
    input binary;
    output bcd;
    
    wire w0,w1,w2,w3;
    assign w0 = binary;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    add3 (.in(w2<<1), .out(w3));
    assign bcd = w3;
endmodule

module add3( in, out);
    input in;
    output out;
    reg out;
    
    always@(in)
    begin
        out = in;
        if(in>4) out = out + 3;
        if(in>4) out = out + 3;
    end
endmodule