Forum Discussion
Honored Contributorbig design uses few resources
I compiled a design a few days ago with a Compilation Report like this:
Combinational ALUTs 52,437 Memory ALUTs 0 dedicated logic registers 31,310 Total registers 31,310 ... Total block memory bits 456,312 Today, I compiled a similar one with some IPs added. When I finished the compilation successfully, I got a Compilation Report like this: Combinational ALUTs 671/650,440(< 1%) Memory ALUTs 0/325,220(0%) dedicated logic registers 1187/650,440(<1%) Total registers 1187 ... Total block memory bits 6,200/23,685,120(<1%) I don't know why this happened. The design occupied too few resources. Can anyone tell me? Thanks a lot!12 Replies
Altera_ForumThe debugger runs through jtag and is an output, so the logic that drives it should not be synthesized out. Quartus removes logic when it doesn't drive anything at all. The other thing that happens is things can get synthesized out due to something not hooked up right or something like that.
One trick is to use Design Partitions if you have a license for them. Put on a hierarchy, they keep all the inputs and outputs and therefore the internal logic. (You actually have to have one output of the partition drive logic or a top-level output, otherwise it will get removed). But that is probably not going to to work, as Quartus is removing the logic for a reason, i.e. it doesn't affect the output of your debugger. Keeping the logic through partitions probably won't fix the problem.- Altera_Forum
Add a one bit output PIO to your system and assign the output to a virtual pin using the assignment editor. If you need to configure your design into a device then you'll need to assign that PIO to a real pin (cut the output path since this is a dummy connection as far as you are concerned)
There are preserve attributes that Quartus uses to preserve logic instead of optimizing nets away however this won't work in your case because Nios II is encrypted (plus it would be a lot of work too:)) - Altera_Forum
If you set output pins to virtual, it will assume you will connect it to something later and keep it there. It wont be of use for a real system though - you will have to connect it to something to run it on a real chip. but at least you can check the resource usage.
- Altera_Forum
Is there no way in quartus to have it instantiate all units regardless of whether there are outputs or a debugger? I encountered this problem again even with a debugger in my processors.
All I want is a system where I can run some software on top and my custom instruction will return a result. I don't need any external outputs, etc. - Altera_Forum
A JTAG UART hooked up to the data master should do the trick. The reason why most of the logic is optimized away even with the JTAG debug module is because it is so tightly connected to the CPU that most of the CPU logic doesn't drive logic that goes anywhere and you saw the result of this (hardly any logic remaining).
By the way when debugging this type of thing I recommend adding columns to the hierachy view in Quartus so that you can see the resource usage at each level of the design heirarchy. It sometimes gives you a hint of what caused the logic to be synthesized away. Like others have said things like disconnected outputs, hardcoded inputs, etc... will cause this to occur and Quartus will emit messages about this. - Altera_Forum
oh, whoops! The only things in my design are on-chip memory and a bunch of processors with custom instructions added, and I'm using SOPC builder, not Qsys if that makes any difference. I've also already made another system with just one processor while trying this out.
I guess what I don't understand is - I don't need any external outputs for anything (that I am aware of), so what kind of outputs would I create just so that I have outputs in the system and it doesn't optimize the design away? - Altera_Forum
Actually what I mean is what else is in the system? Also while debugging this I would reduce your system down to a single Nios II core. If you system fits well into a screen shot then you could attach that the the post.
- Altera_Forum
I'm using the NIOS II - F cores in my system. I've also tried it using the 'S' cores, but they created clock and reset outputs for every cpu and I wasn't sure what to do with them?
- Altera_Forum
If your system only had a clock and reset input, by removing the debug modules you no longer have any outputs which will cause everything to be optimized away. With the debug logic you had outputs through JTAG which are not visible but they are present when you have a JTAG debug module or debug core (or signaltap or any other JTAG based IP).
I have a hunch what is going on, but before I say it let us know what cores are in your system. - Altera_Forum
I am having the same issue. I created a system with multiple processors each having a level 1 debugger. This design did not optimize away all my modules.
Then, I used the same system but removed the debugger from each processor. This design optimized away all my modules. I've taken a look at the .map.rpt file and it certainly shows a lot of removed logic, but I'm not sure what connections I need to make. The only connections to my system (nios_system) are two inputs (clk, and reset_n). These are both connected (I believe?) in my top level module where I instantiate the system. Any ideas?
