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Altera_Forum
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14 years ago

big design uses few resources

I compiled a design a few days ago with a Compilation Report like this: Combinational ALUTs 52,437 Memory ALUTs 0 dedicated logic registers 31,310 T...
Altera_Forum's avatar
Altera_Forum
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14 years ago

If your system only had a clock and reset input, by removing the debug modules you no longer have any outputs which will cause everything to be optimized away. With the debug logic you had outputs through JTAG which are not visible but they are present when you have a JTAG debug module or debug core (or signaltap or any other JTAG based IP).

I have a hunch what is going on, but before I say it let us know what cores are in your system.