big design uses few resources

A JTAG UART hooked up to the data master should do the trick. The reason why most of the logic is optimized away even with the JTAG debug module is because it is so tightly connected to the CPU that most of the CPU logic doesn't drive logic that goes anywhere and you saw the result of this (hardly any logic remaining).

By the way when debugging this type of thing I recommend adding columns to the hierachy view in Quartus so that you can see the resource usage at each level of the design heirarchy. It sometimes gives you a hint of what caused the logic to be synthesized away. Like others have said things like disconnected outputs, hardcoded inputs, etc... will cause this to occur and Quartus will emit messages about this.