Hi, I am working on Altera FPGA. Please help me to code a Bidirectional bus using HDL. Can anyone share a code for this. Regards, freak

which HDL? AHDL, VHDL or Verilog?

For example, this could be a sample code for VHDL (I wrote it without checking for syntax errors, be warned) entity io_buffer is port ( data_out : in std_logic_vector(WIDTH-1 downto 0); data_in : out std_logic_vector(WIDTH-1 downto 0); data_out_ena : in std_logic; io_data : inout std_logic_vector(WIDTH-1 downto 0) ); end io_buffer; architecture arch of io_buffer is begin bidir_buffer : process (data_out_ena, io_data) begin if (data_out_ena = '1') then io_data <= data_out; else io_data <= (others => '0'); end if; data_in <= io_data; end process bidir_buffer; end arch;

I think you meant io_data <= (others => 'Z');

Sorry. You are right, Tricky. As I said I wrote the code without checking

Thanks Triky, Cris. Can i use the same code if i target for FPGA and ASIC. My doubt is, do i need to modify 'Z' if using in either ASIC or FPGA. Regards, freak

Bidirectional buffer | Altera Community

14 Replies

Altera_Forum
Honored Contributor
12 years ago
'X' means the signal has an undefined state. This is because when data_out_ena = '0', io_data is tristated and it's supposed to be driven by an external source. If you dont' specify any external signal, data_in state is indeed undefined.
Altera_Forum
Honored Contributor
12 years ago
Thanks Cris72 for the feedback.

However, I have already defined my io_data to be 'Z' in the testbench but the problem is the data_in is 'X' instead of Z when in tri-state condition. Any other possible root cause?
Altera_Forum
Honored Contributor
12 years ago
AFAIK the tristate condition only applies to output drive: the actual signal state depends on other active drivers and in the real world it always switches either low or high according to the physical behaviour of logic gates (CMOS, TTL, presence of pullups or pulldown...). In any case the real signal always falls into a specific state, low or high: there is not a 'tristate' level.
Without an explicit specification, the simulator can't determine what the real signal status will be, then it indeed place it as 'undefined'
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
In any case the real signal always falls into a specific state, low or high.
--- Quote End ---

Not necessarily. A floating pin without pull/up, pull-down or hold circuit might also arbitrarily oscillate between '1' and '0'. 'X' in simulation can be understood as reflecting this unknown state.

--- Quote Start ---
there is not a 'tristate' level.
--- Quote End ---

That's the essential point. 'Z' can't be detected as an input state.

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Bidirectional buffer

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