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Honored Contributor
Honored ContributorBidirectional buffer
Hi, I am working on Altera FPGA. Please help me to code a Bidirectional bus using HDL. Can anyone share a code for this. Regards, freak
Altera_ForumHonored Contributor
Honored ContributorAFAIK the tristate condition only applies to output drive: the actual signal state depends on other active drivers and in the real world it always switches either low or high according to the physical behaviour of logic gates (CMOS, TTL, presence of pullups or pulldown...). In any case the real signal always falls into a specific state, low or high: there is not a 'tristate' level.
Without an explicit specification, the simulator can't determine what the real signal status will be, then it indeed place it as 'undefined'
